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M48T37Y M48T37V
3.3V-5V 256 Kbit (32Kb x8) TIMEKEEPER(R) SRAM
s
INTEGRATED ULTRA-LOW POWER SRAM, REAL TIME CLOCK, POWER-FAIL CONTROL CIRCUIT and BATTERY FREQUENCY TEST OUTPUT for REAL TIME CLOCK SOFTWARE CALIBRATION YEAR 2000 COMPLIANT AUTOMATIC POWER-FAIL CHIP DESELECT and WRITE PROTECTION WATCHDOG TIMER WRITE PROTECT VOLTAGE (VPFD = Power-Fail Deselect Voltage): - M48T37Y: 4.2V VPFD 4.5V - M48T37V: 2.7V VPFD 3.0V
44
SNAPHAT (SH) Battery
s
s s
s s
1
SOH44 (MH)
s
PACKAGING INCLUDES a 44-LEAD SOIC and SNAPHAT TOP (to be Ordered Separately) SOIC PACKAGE PROVIDES DIRECT CONNECTION for a SNAPHAT(R) TOP which CONTAINS the BATTERY and CRYSTAL MICROPROCESSOR POWER-ON RESET (Valid even during battery back-up mode) PROGRAMMABLE ALARM OUTPUT ACTIVE in the BATTERY BACKED-UP BATTERY LOW FLAG
A0-A14 15 VCC 8 DQ0-DQ7 RST IRQ/FT
s
Figure 1. Logic Diagram
s
s
s
Table 1. Signal Names
A0-A14 DQ0-DQ7 RST IRQ/FT WDI E G W VCC VSS NC February 2000 Address Inputs Data Inputs / Outputs Power Fail Reset Output (Open Drain) Interrupt / Frequency Test Output (Open Drain) Watchdog Input Chip Enable Output Enable Write Enable Supply Voltage Ground Not connected Internally 1/20
W E G WDI
M48T37Y M48T37V
VSS
AI02172
M48T37Y, M48T37V
Table 2. Absolute Maximum Ratings (1)
Symbol TA Parameter Grade 1 Ambient Operating Temperature Grade 6 SNAPHAT TSTG T SLD (2) VIO Storage Temperature (VCC Off, Oscillator Off) Lead Solder Temperature for 10 seconds M48T37Y Input or Output Voltages M48T37V M48T37Y V CC IO PD Supply Voltage M48T37V Output Current Power Dissipation -0.3 to 4.6 10 1 V mA W -0.3 to 4.6 -0.3 to 7 V V SOIC -40 to 85 -40 to 85 -55 to 125 260 -0.3 to 7 Value 0 to 70 Unit C C C C C V
Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect reliability. 2. Soldering temperature not to exceed 260C for 10 seconds (total thermal budget not to exceed 150C for longer than 30 seconds).
CAUTION: Negative undershoots below -0.3V are not allowed on any pin while in the Battery Back-up mode. CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPH AT sockets.
Figure 2. SOIC Connections
NC RST NC NC A14 A12 A7 A6 A5 A4 A3 NC NC WDI A2 A1 A0 DQ0 DQ1 DQ2 NC VSS
1 44 2 43 3 42 4 41 5 40 6 39 7 38 8 37 9 36 35 10 11 M48T37Y 34 12 M48T37V 33 13 32 14 31 15 30 16 29 17 28 18 27 19 26 20 25 21 24 22 23
AI02174
VCC NC NC NC IRQ/FT W A13 A8 A9 A11 G NC NC A10 E NC DQ7 DQ6 DQ5 DQ4 DQ3 NC
DESCRIPTION The M48T37Y/37V TIMEKEEPER(R) RAM is a 32Kb x8 non-volatile static RAM and real time clock. The monolithic chip is available in a special package which provides a highly integrated battery backed-up memory and real time clock solution. The 44 lead 330mil SOIC package provides sockets with gold-plated contacts at both ends for direct connection to a separate SNAPHAT housing containing the battery and crystal. The unique design allows the SNAPHAT battery package to be mounted on top of the SOIC package after the completion of the surface mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery and crystal damage due to the high temperatures required for device surface-mounting. The SNAPHAT housing is keyed to prevent reverse insertion. The SOIC and battery packages are shipped separately in plastic anti-static tubes or in Tape &Reel form. For the 44 lead SOIC, the battery/crystal package (i.e. SNAPHAT) part number is "M4T28BR12SH" or "M4T32-BR12SH". Caution: Do not place the SNAPHAT battery/crystal top in conductive foam, as this will drain the lithium button-cell battery. As Figure 3 shows, the static memory array and the quartz controlled clock oscillator of the M48T37Y/37V are integrated on one silicon chip.
2/20
M48T37Y, M48T37V
Table 3. Operating Modes (1)
Mode Deselect Write Read Read Deselect Deselect VCC 4.5V to 5.5V (M48T37Y) or 3.0V to 3.6V (M48T37V) VSO to VPFD (min) (2) VSO E VIH VIL VIL VIL X X G X X VIL VIH X X W X VIL VIH VIH X X DQ0-DQ7 High Z D IN DOUT High Z High Z High Z Power Standby Active Active Active CMOS Standby Battery Back-up Mode
Note: 1. X = VIH or VIL; VSO = Battery Back-up Switchover Voltage. 2. See Table 7 for details.
Figure 3. Block Diagram
IRQ/FT
WDI
OSCILLATOR AND CLOCK CHAIN 32,768 Hz CRYSTAL POWER 16 x 8 BiPORT SRAM ARRAY
A0-A14
LITHIUM CELL VOLTAGE SENSE AND SWITCHING CIRCUITRY VPFD
32,752 x 8 SRAM ARRAY
DQ0-DQ7
E W G
VCC
RST
VSS
AI03253
3/20
M48T37Y, M48T37V
Table 4. AC Measurement Conditions
Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 5ns 0 to 3V 1.5V
DEVICE UNDER TEST 645
Figure 4. AC Testing Load Circuit
Note that Output Hi-Z is defined as the point where data is no longer driven.
The memory locations, to provide user accessible BYTEWIDETM clock information are in the bytes with addresses 7FF1 and 7FF9h-7FFFh (located in Table 11). The clock locations contain the century, year, month, date, day, hour, minute, and second in 24 hour BCD format. Corrections for 28, 29 (leap year-compliant until the year 2100), 30, and 31 day months are made automatically. Byte 7FF8h is the clock control register. This byte controls user access to the clock information and also stores the clock calibration setting. Byte 7FF7h contains the watchdog timer setting. The watchdog timer redirects an out-of-control microprocessor and provides a reset or interrupt to it. Byte 7FF2h-7FF5h are reserved for clock alarm programming. These bytes can be used to set the alarm. This will generate an active low signal on the IRQ/FT pin when the alarm bytes match the date, hours, minutes and seconds of the clock. The eight clock bytes are not the actual clock counters themselves; they are memory locations consisting of BiPORTTM read/write memory cells. The M48T37Y/ 37V includes a clock control circuit which updates the clock bytes with current information once per second. The information can be accessed by the user in the same manner as any other location in the static memory array. The M48T37Y/37V also has its own Power-fail Detect circuit. The control circuitry constantly monitors the single VCC supply for an out of tolerance condition. When VCC is out of tolerance, the circuit writes protects the SRAM, providing a high degree of data security in the midst of unpredictable system operation brought on by low VCC. As VCC falls below the Battery Back-up Switchover Voltage (VSO), the control circuitry connects the battery which maintains data and clock operation until valid power returns.
CL = 100pF
1.75V
CL includes JIG capacitance
AI02325
Note: Excluding open-drain output pins.
READ MODE The M48T37Y/37V is in the Read Mode whenever Write Enable (W) is high and Chip Enable (E) is low. The unique address specified by the 15 Address Inputs defines which one of the 32,752 bytes of data is to be accessed. Valid data will be available at the Data I/O pins within Address Access time (t AVQV) after the last address input signal is stable, providing that the E and Output Enable (G) access times are also satisfied. If the E and G access times are not met, valid data will be available after the latter of the Chip Enable Access time (tELQV) or Output Enable Access time (tGLQV). The state of the eight three-state Data I/O signals is controlled by E and G. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the Address Inputs are changed while E and G remain active, output data will remain valid for Output Data Hold time (t AXQX) but will be indeterminate until the next Address Access.
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M48T37Y, M48T37V
Table 5. Capacitance (1, 2) (TA = 25 C)
Symbol C IN CIO (3) Parameter Input Capacitance Input / Output Capacitance Test Condit ion VIN = 0V VOUT = 0V Min Max 10 10 Unit pF pF
Note: 1. Effective capacitance measured with power supply at 5V. 2. Sampled only, not 100% tested. 3. Outputs deselected.
Table 6. DC Characteristics (TA = 0 to 70 C or -40 to 85 C)
M48T37Y Symbol Parameter Test Condition VCC = 4.5V to 5.5V Min ILI (1) ILO (1) ICC ICC1 ICC2 VIL (2) VIH VOL VOL VOH (2) Input Leakage Current Output Leakage Current Supply Current Supply Current (Standby) TTL Supply Current (Standby) CMOS Input Low Voltage Input High Voltage Output Low Voltage (standard) Output Low Voltage (open drain) Output High Voltage IOL = 2.1mA IOL = 10mA I OH = -1mA 2.4 0V VIN V CC 0V VOUT VCC Outputs open E = VIH E = VCC - 0.2V -0.3 2.2 Max 1 1 50 3 3 0.8 VCC + 0.3 0.4 0.4 2.4 -0.3 2.2 M48T37V VCC = 3.0V to 3.6V Min Max 1 1 33 2 2 0.8 VCC + 0.3 0.4 0.4 A A mA mA mA V V V V V Unit
Note: 1. Outputs deselected. 2. Negative spikes of -1V allowed for up to 10ns once per cycle.
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M48T37Y, M48T37V
Table 7. Power Down/Up Trip Points DC Characteristics (1) (TA = 0 to 70 C or -40 to 85 C)
Symbol VPFD Parameter M48T37Y Power-fail Deselect Voltage M48T37V M48T37Y VSO Battery Back-up Switchover Voltage M48T37V Grade 1 tDR Expected Data Retention Time (25C) Grade 6 10 (2) YEARS 5 V PFD -100mV 7 V YEARS 2.7 2.9 VBAT 3.0 V V Min 4.2 Typ 4.4 Max 4.5 Unit V
Note: 1. All voltages referenced to VSS. 2. Using larger M4T32-BR12SH6 SNAPHAT top (recommended for Industrial Temperature Range - grade 6 device).
Table 8. Power Down/Up AC Characteristics (TA = 0 to 70 C or -40 to 85 C)
Symbol tF
(1)
Parameter V PFD (max) to VPFD (min) VCC Fall Time V PFD (min) to VSS VCC Fall Time V PFD (min) to VPFD (max) VCC Rise Time V SS to VPFD (min) VCC Rise Time V PFD (max) to RST High M48T37Y M48T37V
Min 300 10 150 10 1 40
Max
Unit s s s s s
tFB (2) tR tRB tREC (3)
200
ms
Note: 1. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200s after VCC passes VPFD (min). 2. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data. 3. tREC (min) = 20ms for Industrial Temperature Range - grade 6 device.
Figure 5. Power Down/Up Mode AC Waveforms
VCC VPFD (max) VPFD (min) VSO tF tFB tDR tREC RST tRB tR
INPUTS
VALID
DON'T CARE
VALID
HIGH-Z OUTPUTS VALID VALID
AI03078
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M48T37Y, M48T37V
Figure 6. Read Mode AC Waveforms.
tAVAV A0-A14 tAVQV tELQV E tELQX tGLQV G tGLQX DQ0-DQ7 VALID
AI00925
VALID tAXQX tEHQZ
tGHQZ
Note: Write Enable (W) = High.
Table 9. Read Mode AC Characteristics (TA = 0 to 70 C or -40 to 85 C)
M48T37Y Symbol Parameter V CC = 4.5V to 5.5V -70 Min tAVAV tAVQV (1) tELQV (1) tGLQV (1) tELQX (2) tGLQX (2) tEHQZ (2) tGHQZ (2) tAXQX (1) Read Cycle Time Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable Low to Output Transition Output Enable Low to Output Transition Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition 10 5 5 25 25 10 70 70 70 35 10 5 50 40 Max Min 100 100 100 50 M48T37V VCC = 3.0V to 3.6V -10 Max ns ns ns ns ns ns ns ns ns Unit
Note: 1. CL = 100pF. 2. CL = 5pF.
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M48T37Y, M48T37V
Figure 7. Write Enable Controlled, Write AC Waveform
tAVAV A0-A14 VALID tAVWH tAVEL E tWLWH tAVWL W tWLQZ tWHDX DQ0-DQ7 DATA INPUT tDVWH
AI00926
tWHAX
tWHQX
WRITE MODE The M48T37Y/37V is in the Write Mode whenever W and E are low. The start of a write is referenced from the latter occurring falling edge of W or E. A write is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for a minimum of tEHAX from Chip Enable or tWHAX from Write Enable prior to the initiation of another read or write cycle. Data-in must be valid t DVWH prior to the end of write and remain valid for tWHDX afterward. G should be kept high during write cycles to avoid bus contention; although, if the output bus has been activated by a low on E and G a low on W will disable the outputs tWLQZ after W falls. DATA RETENTION MODE With valid VCC applied, the M48T37Y/37V operates as a conventional BYTEWIDE static RAM. Should the Supply Voltage decay, the RAM will automatically power-fail deselect, write protecting itself when VCC falls within the VPFD (max), VPFD (min) window. All outputs become high impedance, and all inputs are treated as "don't care".
Note: A power failure during a write cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the RAM's content. At voltages below VPFD (min), the user can be assured the memory will be in a write protected state, provided the VCC fall time is not less than tF. The M48T37Y/37V may respond to transient noise spikes on VCC that reach into the deselect window during the time the device is sampling VCC. Therefore, decoupling of the power supply lines is recommended. When VCC drops below VSO, the control circuit switches power to the internal battery which preserves data and powers the clock. The internal button cell will maintain data in the M48T37Y/37V for an accumulated period of at least 7 years at room temperature when VCC is less than VSO. As system power returns and VCC rises above VSO, the battery is disconnected, and the power supply is switched to external V CC. Normal RAM operation can resume tREC after VCC reaches VPFD (max). For more information on Battery Storage Life refer to the Application Note AN1012.
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M48T37Y, M48T37V
Table 10. Write Mode AC Characteristics (TA = 0 to 70 C or -40 to 85 C)
M48T37Y VCC = 4.5V to 5.5V Symbol Parameter -70 Min tAVAV tAVWL tAVEL tWLWH tELEH tWHAX tEHAX tDVWH tDVEH tWHDX tEHDX tWLQZ (1, 2) tAVWH tAVEH tWHQX (1, 2) Write Cycle Time Address Valid to Write Enable Low Address Valid to Chip Enable Low Write Enable Pulse Width Chip Enable Low to Chip Enable High Write Enable High to Address Transition Chip Enable High to Address Transition Input Valid to Write Enable High Input Valid to Chip Enable High Write Enable High to Input Transition Chip Enable High to Input Transition Write Enable Low to Output Hi-Z Address Valid to Write Enable High Address Valid to Chip Enable High Write Enable High to Output Transition 60 60 5 70 0 0 50 55 0 0 30 30 5 5 25 80 80 10 Max Min 100 0 0 80 80 10 10 50 50 5 5 50 -10 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns M48T37V VCC = 3.0V to 3.6V Unit
Note: 1. CL = 5pF. 2. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
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M48T37Y, M48T37V
Figure 8. Chip Enable Controlled, Write AC Waveforms
tAVAV A0-A14 VALID tAVEH tAVEL E tAVWL W tEHDX DQ0-DQ7 DATA INPUT tDVEH
AI00927
tELEH
tEHAX
Figure 9. Clock Calibration
NORMAL
POSITIVE CALIBRATION
NEGATIVE CALIBRATION
AI00594B
POWER-ON RESET The M48T37Y/37V continuously monitors VCC. When VCC falls to the power fail detect trip point, the RST pulls low (open drain) and remains low on power-up for 40ms to 200ms after VCC passes VPFD. RST is valid for all VCC conditions. The RST pin is an open drain output and an appropriate resistor to VCC should be chosen to control rise time. PROGRAMMABLE INTERRUPTS The M48T37Y/37V provides two programmable interrupts; an alarm and a watchdog. When an interrupt condition occurs, the M48T37Y/37V sets the appropriate flag bit in the flag register 7FF0h. The interrupt enable bits in (AFE and ABE) in
7FF6h and the Watchdog Steering (WDS) bit in 7FF7h allow the interrupt to activate the IRQ/FT pin. The interrupt flags and the IRQ/FT output are cleared by a read to the flags register. An interrupt condition reset will not occur unless the addresses are stable at the flag location for at least 15ns while the device is in the read mode as shown in Figure 11. The IRQ/FT pin is an open drain output and requires a pull-up resistor (10k recommended) to VCC. The pin remains in the high impedance state unless an interrupt occurs or the frequency test mode is enabled.
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M48T37Y, M48T37V
Table 11. Register Map
Data Address D7 7FFFh 7FFEh 7FFDh 7FFCh 7FFBh 7FFAh 7FF9h 7FF8h 7FF7h 7FF6h 7FF5h 7FF4h 7FF3h 7FF2h 7FF1h 7FF0h
Keys:
D6
D5
D4
D3
D2 Year
D1
D0
Functio n/Range BCD Format Year Month Date Day Hour Min Sec Control 00-99 01-12 01-31 01-7 00-23 00-59 00-59
10 Years 0 0 0 0 0 ST W WDS AFE RPT4 RPT3 RPT2 RPT1 R BMB4 0 0 0 0 0 FT 0 0 0 10 M 10 Date 0 0
Month Date: Day of Month Day of Week Hours Minutes Seconds Calibration
10 Hours 10 Minutes 10 Seconds S BMB3 ABE BMB2 0 BMB1 0
BMB0 0
RB1 0
RB0 0
Watchdog Interrupts Alarm Date Alarm Hour Alarm Min Alarm Sec Century 01-31 00-23 00-59 00-59 00-99
AIarm 10 Date AIarm 10 Hours Alarm 10 Minutes Alarm 10 Seconds
Alarm Date Alarm Hours Alarm Minutes Alarm Seconds 100 Year
1000 Year WDF AF Z BL Z
Z
Z
Z
Flags
S = Sign Bit FT = Frequency Test Bit R = Read Bit W = Write Bit ST = Stop Bit 0 = Must be set to '0' BL = Battery Low Flag BMB0-BMB4 = Watchdog Multiplier Bits
AFE = Alarm Flag Enable Flag RB0-RB1 = Watchdog Resolution Bits WDS = Watchdog Steering Bit ABE = Alarm in Battery Back-Up Mode Enable Bit RPT1-RPT4 = Alarm Repeat Mode Bits WDF = Watchdog Flag AF = Alarm Flag Z = '0' and are Read only
CLOCK OPERATIONS Reading the Clock Updates to the TIMEKEEPER registers should be halted before clock data is read to prevent reading data in transition. Because the BiPORT TIMEKEEPER cells in the RAM array are only data registers, and not the actual clock counters, updating the registers can be halted without disturbing the clock itself. Updating is halted when a `1' is written to the READ bit, D6 in the Control Register 7FF8h. As long as a `1' remains in that position, updating is halted. After a halt is issued, the registers reflect the count; that is, the day, date, and the time that were current at the moment the halt command was issued. All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an update in
progress. Updating will resume within a second after the bit is reset to a '0'. Setting the Clock Bit D7 of the Control Register (7FF8h) is the WRITE bit. Setting the WRITE bit to a `1', like the READ bit, halts updates to the TIMEKEEPER registers. The user can then load them with the correct day, date, and time data in 24 hour BCD format (see Table 11). Resetting the WRITE bit to a `0' then transfers the values of all time registers (7FF1h, 7FF9h-7FFFh) to the actual TIMEKEEPER counters and allows normal operation to resume. After the WRITE bit is reset, the next clock update will occur in approximately one second. Note: Upon power-up following a power failure, both the WRITE bit and the READ bit will be reset to '0'.
11/20
M48T37Y, M48T37V
Figure 10. Crystal Accuracy Across Temperature
Frequency (ppm) 20 0 -20 -40 -60 -80 -100 -120 -140 -160 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 F = -0.038 ppm (T - T )2 10% 0 F C2 T0 = 25 C
Temperature C
AI00999
Stopping and Starting the Oscillator The oscillator may be stopped at any time. If the device is going to spend a significant amount of time on the shelf, the oscillator can be turned off to minimize current drain on the battery. The STOP bit is the MSB of the seconds register. Setting it to a `1' stops the oscillator. When reset to a '0', the M48T37Y/37V oscillator starts within one second. Note: It is not necessary to set the WRITE bit when setting or resetting the FREQUENCY TEST bit (FT) or the STOP bit (ST). Calibrating the Clock The M48T37Y/37V is driven by a quartz controlled oscillator with a nominal frequency of 32,768 Hz. The devices are tested not to exceed 35 ppm (parts per million) oscillator frequency error at 25 C, which equates to about 1.53 minutes per month. With the calibration bits properly set, the accuracy of each M48T37Y/37V improves to better than +1/-2 ppm at 25 C. The oscillation rate of any crystal changes with temperature (see Figure 10). Most clock chips compensate for crystal frequency and temperature shift error with cumbersome trim capacitors. The M48T37Y/37V design, however, employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in Fig-
ure 9. The number of times pulses are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five bit Calibration byte found in the Control Register. Adding counts speeds the clock up, subtracting counts slows the clock down. The Calibration byte occupies the five lower order bits (D4-D0) in the Control Register 7FF8h. These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a Sign bit; `1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary `1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125, 829, 120 (64 minutes x 60 seconds/ minute x 32,768 cycles/second) actual oscillator cycles, that is +4.068 or -2.034 ppm of adjustment per calibration step in the calibration register. Assuming that the oscillator is in fact running at exactly 32,768 Hz, each of the 31 increments in the Calibration byte would represent +10.7 or -5.35
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M48T37Y, M48T37V
Figure 11. Interrupt Reset Waveforms
A0-A14
ADDRESS 7FF0h 15ns Min
ACTIVE FLAG BIT
IRQ/FT
AI01677B
seconds per month which corresponds to a total range of +5.5 or -2.75 minutes per month. Two methods are available for ascertaining how much calibration a given M48T37Y/37V may require. The first involves simply setting the clock, letting it run for a month and comparing it to a known accurate reference (like WWW broadcasts). While that may seem crude, it allows the designer to give the end user the ability to calibrate his clock as his environment may require, even after the final product is packaged in a non-user serviceable enclosure. All the designer has to do is provide a simple utility that accesses the Calibration byte. The second approach is better suited to a manufacturing environment, and involves the use of the IRQ/FT pin. The pin will toggle at 512Hz when the Stop bit (ST, D7 of 7FF9h) is `0', the Frequency Test Bit (FT, D6 of 7FFCh) is `1', the Alarm Flag Enable Bit (AFE, D7 of 7FF6h) is `0', and the Watchdog Steering bit (WDS, D7 of 7FF7h) is `1' or the Watchdog Register is reset (7FF7h=0). Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.01024 Hz would indicate a +20 ppm oscillator frequency error, requiring a -10(WR001010) to be loaded into the Calibration Byte for correction. Note that setting or changing the Calibration Byte does not affect the Frequency test output frequency. The IRQ/FT pin is an open drain output which requires a pull-up resistor for proper operation. A 500-10k resistor is recommended in order to control the rise time. The FT bit is cleared on power-down. For more information on calibration, see the Application Note AN934 "TIMEKEEPER Calibration".
SETTING ALARM CLOCK Registers 7FF5h-7FF2h contain the alarm settings. The alarm can be configured to go off at a predetermined time on a specific day of the month or repeat every day, hour, minute, or second. It can also be programmed to go off while the M48T37Y/37V is in the battery back-up mode of operation to serve as a system wake-up call. RPT1-RPT4 put the alarm in the repeat mode of operation. Table 12 shows the possible configurations. Codes not listed in the table default to the once per second mode to quickly alert the user of an incorrect alarm setting. Note: User must transition address (or toggle chip enable) to see Flag bit change. When the clock information matches the alarm clock settings based on the match criteria defined by RPT1-RPT4, AF is set. If AFE is also set, the alarm condition activates the IRQ/FT pin. To disable alarm, write '0' to the Alarm Date registers and RPT1-4. The alarm flag and the IRQ/FT output are cleared by a read to the Flags register. The IRQ/FT pin can also be activated in the battery back-up mode. The IRQ/FT will go low if an alarm occurs and both Alarm in Battery Back-up Mode Enable (ABE) and AFE are set. The ABE and AFE bits are reset during power-up, therefore an alarm generated during power-up will only set AF. The user can read the Flag Register at system boot-up to determine if an alarm was generated while the M48T37Y/37V was in the deselect mode during power-up. Figure 12 illustrates the back-up mode alarm timing.
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M48T37Y, M48T37V
Figure 12. Back-up Mode Alarm Waveforms
tREC VCC VPFD (max) VPFD (min) VSO
ABE, AFE bit in Interrupt Register
AF bit in Flags Register
IRQ/FT HIGH-Z HIGH-Z
AI03254B
Table 12. Alarm Repeat Mode
RPT4 1 1 1 1 0 RPT3 1 1 1 0 0 RPT2 1 1 0 0 0 RPT1 1 0 0 0 0 Alarm Activated Once per Second Once per Minute Once per Hour Once per Day Once per Month
WATCHDOG TIMER The watchdog timer can be used to detect an outof-control microprocessor. The user programs the watchdog timer by setting the desired amount of time-out into the eight bit Watchdog Register, address 7FF7h. The five bits (BMB4-BMB0) store a binary multiplier and the two lower order bits (RB1RB0) select the resolution, where 00 = 1/16 second, 01 = 1/4second, 10 = 1 second, and 11 = 4 seconds. The amount of time-out is then determined to be the multiplication of the five bit multiplier value with the resolution. (For example: writing 00001110 in the Watchdog Register = 3x1 or 3 seconds). Note: Accuracy of timer is within the selected resolution.
If the processor does not reset the timer within the specified period, the M48T37Y/37V sets the Watchdog Flag (WDF) and generates a watchdog interrupt or a microprocessor reset. WDF is reset by reading the Flags Register (Address 1FF0h). The most significant bit of the Watchdog Register is the Watchdog Steering Bit. When set to a `0', the watchdog will activate the IRQ/FT pin when timedout. When WDS is set to a `1', the watchdog will output a negative pulse on the RST pin for a duration of 40ms to 200ms. The Watchdog register and the FT bit will reset to a '0' at the end of a Watchdog time-out when the WDS bit is set to a `1'. The watchdog timer resets when the microprocessor performs a re-write of the Watchdog Register or an edge transition, (low to high / high to low) on the WDI pin occurs. The time-out period then starts over. The watchdog timer is disabled by writing a value of 00000000 to the eight bits in the Watchdog Register. Should the watchdog timer time out, a value of 00h needs to be written to the Watchdog Register in order to clear the IRQ/FT pin. The watchdog function is automatically disabled upon power-down and the Watchdog Register is cleared. If the watchdog function is set to output to the IRQ/FT pin and the frequency test function is activated, the watchdog or alarm function prevails and the frequency test function is denied. The WDI pin should be connected to VSS if not used.
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M48T37Y, M48T37V
Table 13. Default Values
Conditio n Initial Power-up (Battery Attach for SNAPHAT) (2) Subsequent Power-up / RESET (3) Power-down (4)
Note: 1. 2. 3. 4.
W 0 0 0
R 0 0 0
FT 0 0 0
AFE 0 0 1
ABE 0 0 1
WATCHDOG Register (1) 0 0 0
WDS, BMB0-BMB4, RBO, RB1. State of other control bits undefined. State of other control bits remains unchanged. Assuming these bits set to '1' prior to power-down.
Figure 13. Supply Voltage Protection
VCC VCC
applied to the device. Thus applications which require extensive durations in the battery back-up mode should be powered-up periodically (at least once every few months) in order for this technique to be beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon power-up via a checksum or other technique. POWER-ON DEFAULTS Upon application of power to the device, the following register bits are set to a '0' state: WDS; BMB0-BMB4; RB0-RB1; AFE; ABE; W; R; FT. (See Table 13). POWER SUPPLY DECOUPLING and UNDERSHOOT PROTECTION ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store energy, which stabilizes the VCC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1F (as shown in Figure 13) is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values below VSS by as much as one Volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, it is recommended to connect a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount.
0.1F
DEVICE
VSS
AI02169
BATTERY LOW FLAG The M48T37Y/37V automatically performs periodic battery voltage monitoring upon power-up. The Battery Low Flag (BL), Bit D4 of Flags Register 7FF0h, will be asserted high if the SNAPHAT battery is found to be less than approximately 2.5V. The BL flag will remain active until completion of battery replacement and subsequent battery low monitoring tests, during the next power-up sequence. If a battery low is generated during a power-up sequence, this indicates that the battery voltage is below 2.5V (approximately), which may be insufficient to maintain data integrity. Data should be considered suspect and verified as correct. A fresh battery should be installed. Note: Battery monitoring is a useful technique only when performed periodically. The M48T37Y/37V only monitors the battery when a nominal VCC is
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M48T37Y, M48T37V
Table 14. Ordering Information Scheme
Example: Device Type M48T Supply Voltage and Write Protect Voltage 37Y = V CC = 4.5V to 5.5V; V PFD = 4.2V to 4.5V 37V = V CC = 3.0V to 3.6V; V PFD = 2.7V to 3.0V Speed -70 = 70ns -10 = 100ns Package MH (1) = SOH44 Temperature Range 1 = 0 to 70 C 6 = -40 to 85 C Shipping Method for SOIC blank = Tubes TR = Tape & Reel M48T37Y -70 MH 1 TR
Note: 1. The SOIC package (SOH44) requires the battery package (SNAPHAT ) which is ordered separately under the part number "M4TXX-BR12SH1" in plastic tube or "M4TXX-BR12SH1TR" in Tape & Reel form. Caution: Do not place the SNAPHAT battery package "M4TXX-BR12SH1" in conductive foam since will drain the lithium button-cell battery.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
Table 15. Revision History
Date December 1999 02/07/00 First Issue From Preliminary Data to Data Sheet Battery Low Flag paragraph changed 100ns speed class identifier changed (Tables 9, 10 and 14) Revision Details
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M48T37Y, M48T37V
Table 16. SOH44 - 44 lead Plastic Small Outline, 4-socket SNAPHAT, Package Mechanical Data
mm Symb Typ A A1 A2 B C D E e eB H L N CP 0.81 0.05 2.34 0.36 0.15 17.71 8.23 - 3.20 11.51 0.41 0 44 0.10 Min Max 3.05 0.36 2.69 0.46 0.32 18.49 8.89 - 3.61 12.70 1.27 8 0.032 0.002 0.092 0.014 0.006 0.697 0.324 - 0.126 0.453 0.016 0 44 0.004 Typ Min Max 0.120 0.014 0.106 0.018 0.012 0.728 0.350 - 0.142 0.500 0.050 8 inches
Figure 14. SOH44 - 44 lead Plastic Small Outline, 4-socket SNAPHAT, Package Outline
A2 B e
A C eB CP
D
N
E
H A1 L
1 SOH-A
Drawing is not to scale.
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M48T37Y, M48T37V
Table 17. M4T28-BR12SH SNAPHAT Housing for 48 mAh Battery & Crystal, Package Mechanical Data
mm Symb Typ A A1 A2 A3 B D E eA eB L 0.46 21.21 14.22 15.55 3.20 2.03 6.73 6.48 Min Max 9.78 7.24 6.99 0.38 0.56 21.84 14.99 15.95 3.61 2.29 0.018 0.835 0.560 0.612 0.126 0.080 0.265 0.255 Typ Min Max 0.385 0.285 0.275 0.015 0.022 0.860 0.590 0.628 0.142 0.090 inches
Figure 15. M4T28-BR12SH SNAPHAT Housing for 48 mAh Battery & Crystal, Package Outline
A1
A2 A A3
eA D
B eB
L
E
SHTK-A
Drawing is not to scale.
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M48T37Y, M48T37V
Table 18. M4T32-BR12SH SNAPHAT Housing for 120 mAh Battery & Crystal, Package Mechanical Data
mm Symb Typ A A1 A2 A3 B D E eA eB L 0.46 21.21 17.27 15.55 3.20 2.03 8.00 7.24 Min Max 10.54 8.51 8.00 0.38 0.56 21.84 18.03 15.95 3.61 2.29 0.018 0.835 0.680 0.612 0.126 0.080 0.315 0.285 Typ Min Max 0.415 .0335 0.315 0.015 0.022 0.860 .0710 0.628 0.142 0.090 inches
Figure 16. M4T32-BR12SH SNAPHAT Housing for 120 mAh Battery & Crystal, Package Outline
A1
A2 A A3
eA D
B eB
L
E
SHTK-A
Drawing is not to scale.
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M48T37Y, M48T37V
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in lif e support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics (R) 2000 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A . http://w ww.st.com
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